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PC
2007
161views Management» more  PC 2007»
15 years 2 months ago
High performance combinatorial algorithm design on the Cell Broadband Engine processor
The Sony–Toshiba–IBM Cell Broadband Engine (Cell/B.E.) is a heterogeneous multicore architecture that consists of a traditional microprocessor (PPE) with eight SIMD co-process...
David A. Bader, Virat Agarwal, Kamesh Madduri, Seu...
FPL
2003
Springer
95views Hardware» more  FPL 2003»
15 years 7 months ago
A Model for Hardware Realization of Kernel Loops
Abstract. Hardware realization of kernel loops holds the promise of accelerating the overall application performance and is therefore an important part of the synthesis process. In...
Jirong Liao, Weng-Fai Wong, Tulika Mitra
IPPS
2007
IEEE
15 years 8 months ago
Power-Aware Speedup
Power-aware processors operate in various power modes to reduce energy consumption with a corresponding decrease in peak processor throughput. Recent work has shown power-aware cl...
Rong Ge, Kirk W. Cameron
131
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COREGRID
2007
Springer
15 years 8 months ago
Total Exchange Performance Prediction on Grid Environments
One of the most important collective communication patterns used in scientific applications is the complete exchange, also called All-to-All. Although efficient algorithms have b...
Luiz Angelo Steffenel, Emmanuel Jeannot
EUROPAR
2009
Springer
15 years 7 months ago
Distributed Data Partitioning for Heterogeneous Processors Based on Partial Estimation of Their Functional Performance Models
The paper presents a new data partitioning algorithm for parallel computing on heterogeneous processors. Like traditional functional partitioning algorithms, the algorithm assumes ...
Alexey L. Lastovetsky, Ravi Reddy