111 search results - page 5 / 23 » Using Multiple Memory Access Instructions for Reducing Code ... |
DATE
2005
IEEE
14 years 1 months ago
2005
IEEE
As compared to a large spectrum of performance optimizations, relatively little effort has been dedicated to optimize other aspects of embedded applications such as memory space r...
DAC
2005
ACM
14 years 8 months ago
2005
ACM
In many of embedded systems, particularly for those with high data computations, the delay of memory access is one of the major bottlenecks in the system's performance. It ha...
TVLSI
2002
13 years 7 months ago
2002
This paper presents a network flow approach to solving the register binding and allocation problem for multiword memory access DSP processors. In recently announced DSP processors,...
ISCAPDCS
2004
13 years 9 months ago
2004
The cache hierarchy design in existing SMT and superscalar processors is optimized for latency, but not for bandwidth. The size of the L1 data cache did not scale over the past de...
ISCA
2002
IEEE
14 years 19 days ago
2002
IEEE
An increasingly large portion of scheduler latency is derived from the monolithic content addressable memory (CAM) arrays accessed during instruction wakeup. The performance of th...