Switched Processing Systems (SPS) capture the essence of a fundamental resource allocation problem in many modern communication, computer and manufacturing systems involving hetero...
Current instruction fetch policies in SMT processors are oriented towards optimization of overall throughput and/or fairness. However, they provide no control over how individual ...
Francisco J. Cazorla, Peter M. W. Knijnenburg, Riz...
In this paper we present a technique for Worst-Case Execution Time WCET analysis for pipelined processors. Our technique uses a standard simulator instead of special-purpose pipel...
Parameter variation in integrated circuits causes sections of a chip to be slower than others. To prevent any resulting timing errors, designers have traditionally designed for th...
Smruti R. Sarangi, Brian Greskamp, Josep Torrellas
One of the factors affecting the performance of distributed simulation models is the assignment of logical processes to processors. This paper outlines a dynamic allocation scheme...