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ARITH
1999
IEEE
13 years 12 months ago
Reduced Latency IEEE Floating-Point Standard Adder Architectures
The design and implementation of a double precision floating-point IEEE-754 standard adder is described which uses "flagged prefix addition" to merge rounding with the s...
Andrew Beaumont-Smith, Neil Burgess, S. Lefrere, C...
PLDI
2010
ACM
14 years 19 days ago
Z-rays: divide arrays and conquer speed and flexibility
Arrays are the ubiquitous organization for indexed data. Throughout programming language evolution, implementations have laid out arrays contiguously in memory. This layout is pro...
Jennifer B. Sartor, Stephen M. Blackburn, Daniel F...
IOR
2010
114views more  IOR 2010»
13 years 6 months ago
Inventory Management of a Fast-Fashion Retail Network
Working in collaboration with Spain-based retailer Zara, we address the problem of distributing over time a limited amount of inventory across all the stores in a fast-fashion ret...
Felipe Caro, Jérémie Gallien
ATAL
2005
Springer
14 years 1 months ago
Multi-agent decision support via user-modeling
Decision-support requires the gathering and presentation of information, but is subject to many kinds of resource restrictions (e.g. cost, length, time). Individual users differ n...
Terrence Harvey, Keith S. Decker, Sandra Carberry
IPPS
2009
IEEE
14 years 2 months ago
Efficient microarchitecture policies for accurately adapting to power constraints
In the past years Dynamic Voltage and Frequency Scaling (DVFS) has been an effective technique that allowed microprocessors to match a predefined power budget. However, as process...
Juan M. Cebrian, Juan L. Aragón, José...