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ATS
2009
IEEE
142views Hardware» more  ATS 2009»
14 years 2 months ago
Speeding up SAT-Based ATPG Using Dynamic Clause Activation
Abstract—SAT-based ATPG turned out to be a robust alternative to classical structural ATPG algorithms such as FAN. The number of unclassified faults can be significantly reduce...
Stephan Eggersglüß, Daniel Tille, Rolf ...
DATE
1999
IEEE
135views Hardware» more  DATE 1999»
14 years 12 hour ago
Combinational Equivalence Checking Using Satisfiability and Recursive Learning
The problem of checking the equivalence of combinational circuits is of key significance in the verification of digital circuits. In recent years, several approaches have been pro...
João P. Marques Silva, Thomas Glass
AAAI
2000
13 years 9 months ago
Solving Advanced Reasoning Tasks Using Quantified Boolean Formulas
We consider the compilation of different reasoning tasks into the evaluation problem of quantified boolean formulas (QBFs) as an approach to develop prototype reasoning systems us...
Uwe Egly, Thomas Eiter, Hans Tompits, Stefan Woltr...
JAIR
2007
132views more  JAIR 2007»
13 years 7 months ago
New Inference Rules for Max-SAT
Exact Max-SAT solvers, compared with SAT solvers, apply little inference at each node of the proof tree. Commonly used SAT inference rules like unit propagation produce a simpli...
Chu Min Li, Felip Manyà, Jordi Planes
ASPDAC
2000
ACM
102views Hardware» more  ASPDAC 2000»
13 years 11 months ago
Multi-clock path analysis using propositional satisfiability
We present a satisfiability based multi-clock path analysis method. The method uses propositional satisfiability (SAT) in the detection of multi-clock paths. We show a method to re...
Kazuhiro Nakamura, Shinji Maruoka, Shinji Kimura, ...