Sciweavers

610 search results - page 52 / 122
» Using SAT in QBF
Sort
View
VLSID
2010
IEEE
155views VLSI» more  VLSID 2010»
13 years 5 months ago
Synchronized Generation of Directed Tests Using Satisfiability Solving
Directed test generation is important for the functional verification of complex system-on-chip designs. SAT based bounded model checking is promising for counterexample generatio...
Xiaoke Qin, Mingsong Chen, Prabhat Mishra
ICTAI
2002
IEEE
14 years 22 days ago
DSatz: A Directional SAT Solver for Planning
(Appears as a regular paper in the proceedings of IEEE International Conference on Tools with Artificial Intelligence (ICTAI), IEEE Computer Society, Washington D.C, Nov. 2002, p...
Mark Iwen, Amol Dattatraya Mali
AIA
2006
13 years 9 months ago
Speeding Up Model-based Diagnosis by a Heuristic Approach to Solving SAT
Model-based diagnosis of technical systems requires both a simulation machinery and a logic calculus. The former is responsible for the system's behavior analysis, the latter...
Benno Stein, Oliver Niggemann, Theodor Lettmann
JAIR
2008
103views more  JAIR 2008»
13 years 7 months ago
SATzilla: Portfolio-based Algorithm Selection for SAT
It has been widely observed that there is no single "dominant" SAT solver; instead, different solvers perform best on different instances. Rather than following the trad...
Lin Xu, Frank Hutter, Holger H. Hoos, Kevin Leyton...
ISQED
2002
IEEE
175views Hardware» more  ISQED 2002»
14 years 21 days ago
On the Relation between SAT and BDDs for Equivalence Checking
State-of-the-art verification tools are based on efficient operations on Boolean formulas. Traditional manipulation techniques are based on Binary Decision Diagrams (BDDs) and SAT...
Sherief Reda, Rolf Drechsler, Alex Orailoglu