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» Using SAT in QBF
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ICFP
2003
ACM
14 years 7 months ago
Representing reductions of NP-complete problems in logical frameworks: a case study
Under the widely believed conjecture P=NP, NP-complete problems cannot be solved exactly using efficient polynomial time algorithms. Furthermore, any instance of a NP-complete pro...
Carsten Schürmann, Jatin Shah
DATE
2009
IEEE
100views Hardware» more  DATE 2009»
14 years 2 months ago
Increasing the accuracy of SAT-based debugging
Equivalence checking and property checking are powerful techniques to detect error traces. Debugging these traces is a time consuming design task where automation provides help. I...
André Sülflow, Görschwin Fey, C&e...
CSCWD
2009
Springer
14 years 2 months ago
Random stimulus generation with self-tuning
Constrained random simulation methodology still plays an important role in hardware verification due to the limited scalability of formal verification, especially for the large an...
Yanni Zhao, Jinian Bian, Shujun Deng, Zhiqiu Kong
DATE
2008
IEEE
85views Hardware» more  DATE 2008»
14 years 2 months ago
Improved Visibility in One-to-Many Trace Concretization
We present an improved algorithm for concretization of abstract eres in abstraction refinement-based invariant checking. The algorithm maps each transition of the abstract error ...
Kuntal Nanshi, Fabio Somenzi
ATVA
2007
Springer
152views Hardware» more  ATVA 2007»
14 years 1 months ago
Bounded Synthesis
Abstract. The bounded synthesis problem is to construct an implementation that satisfies a given temporal specification and a given bound on the number of states. We present a so...
Sven Schewe, Bernd Finkbeiner