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» Using Simulation to Schedule Manufacturing Resources
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SIGOPS
2010
179views more  SIGOPS 2010»
13 years 1 months ago
Online cache modeling for commodity multicore processors
Modern chip-level multiprocessors (CMPs) contain multiple processor cores sharing a common last-level cache, memory interconnects, and other hardware resources. Workloads running ...
Richard West, Puneet Zaroo, Carl A. Waldspurger, X...
ICPP
2008
IEEE
14 years 1 months ago
Machine Learning Models to Predict Performance of Computer System Design Alternatives
Computer manufacturers spend a huge amount of time, resources, and money in designing new systems and newer configurations, and their ability to reduce costs, charge competitive p...
Berkin Özisikyilmaz, Gokhan Memik, Alok N. Ch...
DAC
2006
ACM
13 years 9 months ago
Systematic software-based self-test for pipelined processors
Software-based self-test (SBST) has recently emerged as an effective methodology for the manufacturing test of processors and other components in systems-on-chip (SoCs). By moving ...
Mihalis Psarakis, Dimitris Gizopoulos, Miltiadis H...
ICRA
2005
IEEE
168views Robotics» more  ICRA 2005»
14 years 19 days ago
Control of Scalable Wet SMA Actuator Arrays
- This paper presents a new control method to drive an array of wet Shape Memory Alloy actuators utilizing a Matrix Manifold and Valve system (MMV). The MMV architecture allows a v...
L. Flemming, Stephen A. Mascaro
INFOCOM
2000
IEEE
13 years 11 months ago
Egress Admission Control
—Allocating resources for multimedia traffic flows with real-time performance requirements is an important challenge for future packet networks. However, in large-scale networks,...
Coskun Cetinkaya, Edward W. Knightly