Ever shrinking device sizes and innovative micro-architectural and circuit design techniques have made it possible to have multi-million transistor systems running at multi-gigahe...
To support dynamic address translation in today's microprocessors, the first-level cache is accessed in parallel with a translation lookaside buffer (TLB). However, this curre...
Abstract— This paper investigates the performance of trading strategies identified through Computational Intelligence techniques. We focus on trading rules derived by Genetic Pr...
Nicos G. Pavlidis, E. G. Pavlidis, Michael G. Epit...
A strategy to implement adaptive routing in irregular networks is presented and analyzed in this work. A simple and widely applicable deadlock avoidance method, applied to a ring ...
This paper discusses implementation of a sequential procedure to construct proportional half-width confidence intervals for a simulation estimator of the steady-state quantiles an...