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ISLPED
2003
ACM
122views Hardware» more  ISLPED 2003»
14 years 24 days ago
A mixed-clock issue queue design for globally asynchronous, locally synchronous processor cores
Ever shrinking device sizes and innovative micro-architectural and circuit design techniques have made it possible to have multi-million transistor systems running at multi-gigahe...
Venkata Syam P. Rapaka, Diana Marculescu
TC
2008
13 years 7 months ago
The Synonym Lookaside Buffer: A Solution to the Synonym Problem in Virtual Caches
To support dynamic address translation in today's microprocessors, the first-level cache is accessed in parallel with a translation lookaside buffer (TLB). However, this curre...
Xiaogang Qiu, Michel Dubois
CEC
2007
IEEE
14 years 1 months ago
Computational intelligence algorithms for risk-adjusted trading strategies
Abstract— This paper investigates the performance of trading strategies identified through Computational Intelligence techniques. We focus on trading rules derived by Genetic Pr...
Nicos G. Pavlidis, E. G. Pavlidis, Michael G. Epit...
JSA
2006
86views more  JSA 2006»
13 years 7 months ago
High-performance adaptive routing for networks with arbitrary topology
A strategy to implement adaptive routing in irregular networks is presented and analyzed in this work. A simple and widely applicable deadlock avoidance method, applied to a ring ...
Valentin Puente, José A. Gregorio, Fernando...
WSC
2001
13 years 9 months ago
Quantile and histogram estimation
This paper discusses implementation of a sequential procedure to construct proportional half-width confidence intervals for a simulation estimator of the steady-state quantiles an...
E. Jack Chen, W. David Kelton