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IPPS
2010
IEEE
13 years 5 months ago
Structuring the execution of OpenMP applications for multicore architectures
Abstract--The now commonplace multi-core chips have introduced, by design, a deep hierarchy of memory and cache banks within parallel computers as a tradeoff between the user frien...
François Broquedis, Olivier Aumage, Brice G...
ISCA
2000
IEEE
63views Hardware» more  ISCA 2000»
13 years 12 months ago
An embedded DRAM architecture for large-scale spatial-lattice computations
Spatial-lattice computations with finite-range interactions are an important class of easily parallelized computations. This class includes many simple and direct algorithms for ...
Norman Margolus
ISSS
2002
IEEE
139views Hardware» more  ISSS 2002»
14 years 13 days ago
Multiprocessor Mapping of Process Networks: A JPEG Decoding Case Study
We present a system-level design and programming method for embedded multiprocessor systems. The aim of the method is to improve the design time and design quality by providing a ...
Erwin A. de Kock
IPPS
2007
IEEE
14 years 1 months ago
An Architectural Framework for Automated Streaming Kernel Selection
Hardware accelerators are increasingly used to extend the computational capabilities of baseline scalar processors to meet the growing performance and power requirements of embedd...
Nikolaos Bellas, Sek M. Chai, Malcolm Dwyer, Dan L...
BIBM
2009
IEEE
218views Bioinformatics» more  BIBM 2009»
14 years 2 months ago
Real-Time Non-rigid Registration of Medical Images on a Cooperative Parallel Architecture
Abstract—Unacceptable execution time of Non-rigid registration (NRR) often presents a major obstacle to its routine clinical use. Parallel computing is an effective way to accele...
Yixun Liu, Andriy Fedorov, Ron Kikinis, Nikos Chri...