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TPHOL
2005
IEEE
14 years 1 months ago
From PSL to LTL: A Formal Validation in HOL
Using the HOL theorem prover, we proved the correctness of a translation from a subset of Accellera’s property specification language PSL to linear temporal logic LTL. Moreover,...
Thomas Tuerk, Klaus Schneider
ICCAD
2004
IEEE
125views Hardware» more  ICCAD 2004»
14 years 4 months ago
Temporal floorplanning using the T-tree formulation
Improving logic capacity by time-sharing, dynamically reconfigurable FPGAs are employed to handle designs of high complexity and functionality. In this paper, we model each task ...
Ping-Hung Yuh, Chia-Lin Yang, Yao-Wen Chang
TIME
2007
IEEE
14 years 1 months ago
Multilingual Extension of Temporal Expression Recognition Using Parallel Corpora
This paper presents the automatic extension of TERSEO to other languages, a knowledge-based system for the recognition and normalization of temporal expressions, originally develo...
Marcel Puchol-Blasco, Estela Saquete, Patricio Mar...
ENTCS
2008
103views more  ENTCS 2008»
13 years 7 months ago
Systematic Semantic Tableaux for PLTL
The better known methods of semantic tableaux for deciding satisfiability in propositional linear temporal logic generate graphs in addition to classical trees. The test of satisf...
Joxe Gaintzarain, Montserrat Hermo, Paqui Lucio, M...
ASPDAC
2004
ACM
120views Hardware» more  ASPDAC 2004»
14 years 28 days ago
Temporal floorplanning using 3D-subTCG
Improving logic capacity by time-sharing, dynamically reconfigurable FPGAs are employed to handle designs of high complexity and functionality. In this paper, we use a novel topo...
Ping-Hung Yuh, Chia-Lin Yang, Yao-Wen Chang, Hsin-...