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TC
2008
13 years 8 months ago
Adaptive Channel Buffers in On-Chip Interconnection Networks - A Power and Performance Analysis
On-chip interconnection networks (OCINs) have emerged as a modular and scalable solution for wire delay constraints in deep submicron VLSI design. OCIN research has shown that the ...
Avinash Karanth Kodi, Ashwini Sarathy, Ahmed Louri
DIALM
2004
ACM
161views Algorithms» more  DIALM 2004»
14 years 17 days ago
Batch conflict resolution algorithm with progressively accurate multiplicity estimation
The wireless connectivity, essential for pervasive computing, has ephemeral character and can be used for creating ad hoc networks, sensor networks, connection with RFID tags etc....
Petar Popovski, Frank H. P. Fitzek, Ramjee Prasad
INFOCOM
1992
IEEE
14 years 27 days ago
An Assessment of State and Lookup Overhead in Routers
The current Internet is based on a stateless (datagram) architecture. However, many recent proposals rely on the maintenance of state information within network routers, leading t...
Deborah Estrin, Danny J. Mitzel
EUROSYS
2006
ACM
14 years 6 months ago
On the road to recovery: restoring data after disasters
—Restoring data operations after a disaster is a daunting task: how should recovery be performed to minimize data loss and application downtime? Administrators are under consider...
Kimberly Keeton, Dirk Beyer 0002, Ernesto Brau, Ar...
MICRO
2009
IEEE
124views Hardware» more  MICRO 2009»
14 years 3 months ago
ZerehCache: armoring cache architectures in high defect density technologies
Aggressive technology scaling to 45nm and below introduces serious reliability challenges to the design of microprocessors. Large SRAM structures used for caches are particularly ...
Amin Ansari, Shantanu Gupta, Shuguang Feng, Scott ...