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» Using a SAT solver to generate checking sequences
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ISCAS
1999
IEEE
106views Hardware» more  ISCAS 1999»
13 years 11 months ago
Test pattern generation for width compression in BIST
The main objectives of Built-In Self Test (BIST) are the design of test pattern generator circuits which achieve the highest fault coverage, require the shortest sequence of test ...
Paulo F. Flores, Horácio C. Neto, K. Chakra...
CCS
2006
ACM
13 years 11 months ago
EXE: automatically generating inputs of death
This paper presents EXE, an effective bug-finding tool that automatically generates inputs that crash real code. Instead of running code on manually or randomly constructed input,...
Cristian Cadar, Vijay Ganesh, Peter M. Pawlowski, ...
SAT
2009
Springer
119views Hardware» more  SAT 2009»
14 years 2 months ago
Boundary Points and Resolution
We use the notion of boundary points to study resolution proofs. Given a CNF formula F, a lit(x)-boundary point is a complete assignment falsifying only clauses of F having the sam...
Eugene Goldberg
ICCAD
2009
IEEE
159views Hardware» more  ICCAD 2009»
13 years 5 months ago
First steps towards SAT-based formal analog verification
Boolean satisfiability (SAT) based methods have traditionally been popular for formally verifying properties for digital circuits. We present a novel methodology for formulating a...
Saurabh K. Tiwary, Anubhav Gupta, Joel R. Phillips...
NDSS
2009
IEEE
14 years 2 months ago
CSAR: A Practical and Provable Technique to Make Randomized Systems Accountable
We describe CSAR, a novel technique for generating cryptographically strong, accountable randomness. Using CSAR, we can generate a pseudo-random sequence and a proof that the elem...
Michael Backes, Peter Druschel, Andreas Haeberlen,...