54 search results - page 3 / 11 » Using a Swap Instruction to Coalesce Loads and Stores |
ISCA
2008
IEEE
14 years 1 months ago
2008
IEEE
Multicore processors have emerged as a powerful platform on which to efficiently exploit thread-level parallelism (TLP). However, due to Amdahl’s Law, such designs will be incr...
PLDI
1994
ACM
13 years 11 months ago
1994
ACM
As microprocessor speeds increase, memory bandwidth is increasing y the performance bottleneck for microprocessors. This has occurred because innovation and technological improvem...
CC
2004
Springer
14 years 23 days ago
2004
Springer
An important issue in embedded systems design is the size of programs. As computing devices decrease in size, yet with more and more functions, better code size optimizations are i...
IEEEPACT
2002
IEEE
14 years 9 days ago
2002
IEEE
Memory dependence prediction allows out-of-order issue processors to achieve high degrees of instruction level parallelism by issuing load instructions at the earliest time withou...
MICRO
2000
IEEE
13 years 11 months ago
2000
IEEE
Silent store instructions write values that exactly match the values that are already stored at the memory address that is being written. A recent study reveals that significant ...