54 search results - page 8 / 11 » Using a Swap Instruction to Coalesce Loads and Stores |
ISCA
2005
IEEE
14 years 29 days ago
2005
IEEE
This paper presents a hardware-based dynamic optimizer that continuously optimizes an application’s instruction stream. In continuous optimization, dataflow optimizations are p...
ICCD
2006
IEEE
14 years 4 months ago
2006
IEEE
Abstract— In this paper, we describe the design and implementation of the primary memory system of the TRIPS processor. To match the aggressive execution bandwidth and support hi...
CAV
2009
Springer
14 years 8 months ago
2009
Springer
Abstract. Pseudo-code descriptions of STMs assume sequentially consistent program execution and atomicity of high-level STM operations like read, write, and commit. These assumptio...
CGO
2005
IEEE
14 years 1 months ago
2005
IEEE
Data speculative optimization refers to code transformations that allow load and store instructions to be moved across potentially dependent memory operations. Existing research w...
CIIA
2009
13 years 8 months ago
2009
This paper describes our experience in processor/threads synchronization using the POSIX API standard for MPSoC virtual applications prototyping. Spin-Lock (Binary Semaphore) imple...