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CHI
2008
ACM
14 years 8 months ago
An error model for pointing based on Fitts' law
For decades, Fitts' law (1954) has been used to model pointing time in user interfaces. As with any rapid motor act, faster pointing movements result in increased errors. But...
Jacob O. Wobbrock, Edward Cutrell, Susumu Harada, ...
ISCA
1994
IEEE
117views Hardware» more  ISCA 1994»
13 years 11 months ago
Evaluating Stream Buffers as a Secondary Cache Replacement
Today's commodity microprocessors require a low latency memory system to achieve high sustained performance. The conventional high-performance memory system provides fast dat...
Subbarao Palacharla, Richard E. Kessler
HPCA
2001
IEEE
14 years 8 months ago
Reducing DRAM Latencies with an Integrated Memory Hierarchy Design
In this papel; we address the severe performance gap caused by high processor clock rates and slow DRAM accesses. We show that even with an aggressive, next-generation memory syst...
Wei-Fen Lin, Steven K. Reinhardt, Doug Burger
ICCD
2005
IEEE
114views Hardware» more  ICCD 2005»
14 years 4 months ago
Memory Bank Predictors
Cache memories are commonly implemented through multiple memory banks to improve bandwidth and latency. The early knowledge of the data cache bank that an instruction will access ...
Stefan Bieschewski, Joan-Manuel Parcerisa, Antonio...
ICC
2007
IEEE
153views Communications» more  ICC 2007»
14 years 2 months ago
Mapping for Iterative MMSE-SIC with Belief Propagation
Abstract— In Multiple-Input Multiple-Output (MIMO) wireless systems, since different signals are transmitted by different antennas simultaneously, interference occurs between the...
Satoshi Gounai, Tomoaki Ohtsuki