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ISCAS
2006
IEEE
93views Hardware» more  ISCAS 2006»
14 years 1 months ago
A low-power clock frequency multiplier
A low-power output feedback controlled frequency synthesizer. Our proposed circuit can be used for low-power multiplier is proposed for Delay Locked Loop (DLL) based application an...
Md. Ibrahim Faisal, Magdy A. Bayoumi, Peiyi Zhao
FPGA
2010
ACM
182views FPGA» more  FPGA 2010»
13 years 5 months ago
A comprehensive approach to modeling, characterizing and optimizing for metastability in FPGAs
Metastability is a phenomenon that can cause system failures in digital circuits. It may occur whenever signals are being transmitted across asynchronous or unrelated clock domain...
Doris Chen, Deshanand Singh, Jeffrey Chromczak, Da...
JECR
2002
120views more  JECR 2002»
13 years 7 months ago
Strategic Connectivity in Extended Enterprise Networks
Extended enterprises are networks of organizations interconnected to exchange critical resources, such as raw materials, labor, access to markets, specialized skills and knowledge...
John Tillquist
GLOBECOM
2006
IEEE
14 years 1 months ago
Further Analysis of XCP Equilibrium Performance
— Low analyzes the equilibrium performance of the recently developed eXplicit Control Protocol (XCP) by applying the derived window-based dynamical model. However, Low’s window...
Peng Wang, David L. Mills
HPDC
2010
IEEE
13 years 8 months ago
Data parallelism in bioinformatics workflows using Hydra
Large scale bioinformatics experiments are usually composed by a set of data flows generated by a chain of activities (programs or services) that may be modeled as scientific work...
Fábio Coutinho, Eduardo S. Ogasawara, Danie...