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» Using the Compiler to Improve Cache Replacement Decisions
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ICCD
2008
IEEE
117views Hardware» more  ICCD 2008»
14 years 4 months ago
Two dimensional highly associative level-two cache design
High associativity is important for level-two cache designs [9]. Implementing CAM-based Highly Associative Caches (CAM-HAC), however, is both costly in hardware and exhibits poor s...
Chuanjun Zhang, Bing Xue
ASPLOS
1992
ACM
13 years 11 months ago
Design and Evaluation of a Compiler Algorithm for Prefetching
Software-controlled data prefetching is a promising technique for improving the performance of the memory subsystem to match today's high-performance processors. While prefet...
Todd C. Mowry, Monica S. Lam, Anoop Gupta
RTSS
2003
IEEE
14 years 28 days ago
Data Caches in Multitasking Hard Real-Time Systems
Data caches are essential in modern processors, bridging the widening gap between main memory and processor speeds. However, they yield very complex performance models, which make...
Xavier Vera, Björn Lisper, Jingling Xue
SIGMOD
2005
ACM
77views Database» more  SIGMOD 2005»
14 years 7 months ago
On Joining and Caching Stochastic Streams
We consider the problem of joining data streams using limited cache memory, with the goal of producing as many result tuples as possible from the cache. Many cache replacement heu...
Jun Yang 0001, Junyi Xie, Yuguo Chen
CC
2002
Springer
131views System Software» more  CC 2002»
13 years 7 months ago
Global Variable Promotion: Using Registers to Reduce Cache Power Dissipation
Global variable promotion, i.e. allocating unaliased globals to registers, can significantly reduce the number of memory operations. This results in reduced cache activity and less...
Andrea G. M. Cilio, Henk Corporaal