467 search results - page 26 / 94 » Using the DEVS Paradigm to Implement a Simulated Processor |
HPCA
2000
IEEE
14 years 1 months ago
2000
IEEE
Value prediction is a technique that breaks true data dependences by predicting the outcome of an instruction, and executes speculatively its data-dependent instructions based on ...
CGF
2005
13 years 8 months ago
2005
The explosive growth in integration technology and the parallel nature of rasterization-based graphics APIs changed the panorama of consumer-level graphics: today, GPUs are cheap,...
ICCD
2005
IEEE
14 years 5 months ago
2005
IEEE
Simultaneous multithreading (SMT) seeks to improve the computation throughput of a processor core by sharing primary resources such as functional units, issue bandwidth, and cache...
DATE
2010
IEEE
14 years 1 months ago
2010
IEEE
—This paper presents reuse-aware modulo scheduling to maximizing stream reuse and improving concurrency for stream-level loops running on stream processors. The novelty lies in t...
ARVLSI
1997
IEEE
14 years 29 days ago
1997
IEEE
This paper describes the architecture and implementation of a high-speed decompression engine for embedded processors. The engine is targeted to processors where embedded programs...