Sciweavers

467 search results - page 78 / 94
» Using the DEVS Paradigm to Implement a Simulated Processor
Sort
View
ISCA
2006
IEEE
130views Hardware» more  ISCA 2006»
13 years 7 months ago
Area-Performance Trade-offs in Tiled Dataflow Architectures
: Tiled architectures, such as RAW, SmartMemories, TRIPS, and WaveScalar, promise to address several issues facing conventional processors, including complexity, wire-delay, and pe...
Steven Swanson, Andrew Putnam, Martha Mercaldi, Ke...
DNA
2006
Springer
110views Bioinformatics» more  DNA 2006»
13 years 11 months ago
DNA Hypernetworks for Information Storage and Retrieval
Content-addressability is a fundamental feature of human memory underlying many associative information retrieval tasks. In contrast to location-based memory devices, content-addre...
Byoung-Tak Zhang, Joo-Kyung Kim
FMCAD
2008
Springer
13 years 9 months ago
BackSpace: Formal Analysis for Post-Silicon Debug
Post-silicon debug is the problem of determining what's wrong when the fabricated chip of a new design behaves incorrectly. This problem now consumes over half of the overall ...
Flavio M. de Paula, Marcel Gort, Alan J. Hu, Steve...
SACI
2009
IEEE
14 years 2 months ago
Experiments on a grid layer prototype for shared data programming model
—In the grid context, there is little support for programming paradigms such as shared data or associative programming. We have previously proposed an original idea to attack sha...
Dacian Tudor, Georgiana Macariu, Wolfgang Schreine...
CHES
2009
Springer
150views Cryptology» more  CHES 2009»
14 years 2 months ago
A Design Flow and Evaluation Framework for DPA-Resistant Instruction Set Extensions
Power-based side channel attacks are a significant security risk, especially for embedded applications. To improve the security of such devices, protected logic styles have been p...
Francesco Regazzoni, Alessandro Cevrero, Fran&cced...