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» Using the DEVS Paradigm to Implement a Simulated Processor
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GLVLSI
2011
IEEE
344views VLSI» more  GLVLSI 2011»
12 years 11 months ago
Circuit design of a dual-versioning L1 data cache for optimistic concurrency
This paper proposes a novel L1 data cache design with dualversioning SRAM cells (dvSRAM) for chip multi-processors (CMP) that implement optimistic concurrency proposals. In this n...
Azam Seyedi, Adrià Armejach, Adrián ...
ICPP
2006
IEEE
14 years 1 months ago
Managing Risk of Inaccurate Runtime Estimates for Deadline Constrained Job Admission Control in Clusters
The advent of service-oriented Grid computing has resulted in the need for Grid resources such as clusters to enforce user-specific service needs and expectations. Service Level ...
Chee Shin Yeo, Rajkumar Buyya
CGO
2003
IEEE
14 years 26 days ago
Retargetable and Reconfigurable Software Dynamic Translation
Software dynamic translation (SDT) is a technology that permits the modification of an executing program’s instructions. In recent years, SDT has received increased attention, f...
Kevin Scott, Naveen Kumar, S. Velusamy, Bruce R. C...
DATE
2010
IEEE
109views Hardware» more  DATE 2010»
14 years 19 days ago
TIMBER: Time borrowing and error relaying for online timing error resilience
Increasing dynamic variability with technology scaling has made it essential to incorporate large design-time timing margins to ensure yield and reliable operation. Online techniq...
Mihir R. Choudhury, Vikas Chandra, Kartik Mohanram...
ASPLOS
1992
ACM
13 years 11 months ago
Design and Evaluation of a Compiler Algorithm for Prefetching
Software-controlled data prefetching is a promising technique for improving the performance of the memory subsystem to match today's high-performance processors. While prefet...
Todd C. Mowry, Monica S. Lam, Anoop Gupta