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TACO
2008
130views more  TACO 2008»
13 years 9 months ago
Efficient hardware code generation for FPGAs
r acceptance of FPGAs as a computing device requires a higher level of programming abstraction. ROCCC is an optimizing C to HDL compiler. We describe the code generation approach i...
Zhi Guo, Walid A. Najjar, Betul Buyukkurt
TC
2008
13 years 9 months ago
Automatic Generation of Modular Multipliers for FPGA Applications
Since redundant number systems allow for constant time addition, they are often at the heart of modular multipliers designed for public key cryptography (PKC) applications. Indeed,...
Jean-Luc Beuchat, Jean-Michel Muller
TVLSI
2008
115views more  TVLSI 2008»
13 years 9 months ago
Outer Loop Pipelining for Application Specific Datapaths in FPGAs
Most hardware compilers apply loop pipelining to increase the parallelism achieved, but pipelining is restricted to the only innermost level in a nested loop. In this work we exten...
Kieron Turkington, Turkington A. Constantinides, K...
INFORMATICALT
2000
114views more  INFORMATICALT 2000»
13 years 9 months ago
The Language-Centric Program Generator Models: 3L Paradigm
Abstract. In this paper we suggest a three-language (3L) paradigm for building the program generator models. The basis of the paradigm is a relationship model of the specification,...
Vytautas Stuikys, Giedrius Ziberkas, Robertas Dama...
DSD
2009
IEEE
93views Hardware» more  DSD 2009»
13 years 7 months ago
Transactions Sequence Tracking by means of Dynamic Binary Instrumentation of TLM Models
Several traditional VHDL fault injection mechanisms like mutants or saboteurs have been adapted to SystemC model descriptions. The main drawback of these approaches is the necessi...
Antonio da Silva, Sebastian Sanchez