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JUCS
2008
181views more  JUCS 2008»
13 years 7 months ago
An IP Core and GUI for Implementing Multilayer Perceptron with a Fuzzy Activation Function on Configurable Logic Devices
: This paper describes the development of an Intellectual Property (IP) core in VHDL able to implement a Multilayer Perceptron (MLP) artificial neural network (ANN) topology with u...
Alfredo Rosado Muñoz, Luis Gómez-Cho...
ISCAS
2008
IEEE
170views Hardware» more  ISCAS 2008»
14 years 2 months ago
Integrated circuit implementation of a cortical neuron
— This paper presents an analogue integrated circuit implementation of a cortical neuron model. The VLSI chip prototype has been implemented in a 0.35 µm CMOS technology. The si...
Jayawan H. B. Wijekoon, Piotr Dudek
IJCES
2002
100views more  IJCES 2002»
13 years 7 months ago
Neural Network Decoders for Linear Block Codes
This paper presents a class of neural networks suitable for the application of decoding error-correcting codes.The neural model is basically a perceptron with a high-order polynom...
Ja-Ling Wu, Yuen-Hsien Tseng, Yuh-Ming Huang
ISCAS
1994
IEEE
104views Hardware» more  ISCAS 1994»
13 years 11 months ago
Stereo Correspondence with Discrete-Time Cellular Neural Networks
In this paper, we propose a new approach of solving the stereopsis problem with a discrete-time cellular neural network(DTCNN) where each node has connectionsonly with its local n...
Sungjun Park, Seung-Jai Min, Soo-Ik Chae
NIPS
2007
13 years 9 months ago
Contraction Properties of VLSI Cooperative Competitive Neural Networks of Spiking Neurons
A non–linear dynamic system is called contracting if initial conditions are forgotten exponentially fast, so that all trajectories converge to a single trajectory. We use contra...
Emre Neftci, Elisabetta Chicca, Giacomo Indiveri, ...