428 search results - page 23 / 86 » Validating High-Level Synthesis |
FDL
2008
IEEE
14 years 21 days ago
2008
IEEE
This paper describes a scenario-based methodology em-level design validation based on the Abstract State Machines formal method. This scenario-based approach complements an existi...
HICSS
1997
IEEE
14 years 3 months ago
1997
IEEE
Business System Engineers, responding to changes in the market place, are faced with the challenge of building increasingly complex and varied systems. Formal approaches and model...
ICFEM
2007
Springer
14 years 5 months ago
2007
Springer
Simulink is popular in industry for modeling and simulating embedded systems. It is deficient to handle requirements of high-level assurance and timing analysis. Previously, we sh...
TSD
2007
Springer
14 years 5 months ago
2007
Springer
Speech synthesis techniques have already reached a high level of naturalness. However, they are often evaluated on text reading tasks. New applications will request for conversatio...
DAC
2012
ACM
12 years 1 months ago
2012
ACM
In this work we address the problem of managing interconnect timing in high-level synthesis by generating a layoutfriendly microarchitecture. A metric called spreading score is pr...