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ICCAD
1997
IEEE
90views Hardware» more  ICCAD 1997»
14 years 20 days ago
A hierarchical decomposition methodology for multistage clock circuits
† This paper describes a novel methodology to automate the design of the interconnect distribution for multistage clock circuits. We introduce two key ideas. First, a hierarchica...
Gary Ellis, Lawrence T. Pileggi, Rob A. Rutenbar
FPGA
2011
ACM
401views FPGA» more  FPGA 2011»
12 years 12 months ago
LegUp: high-level synthesis for FPGA-based processor/accelerator systems
In this paper, we introduce a new open source high-level synthesis tool called LegUp that allows software techniques to be used for hardware design. LegUp accepts a standard C pro...
Andrew Canis, Jongsok Choi, Mark Aldham, Victor Zh...
ASPDAC
2012
ACM
290views Hardware» more  ASPDAC 2012»
12 years 4 months ago
CODA: A concurrent online delay measurement architecture for critical paths
With technology scaling, integrated circuits behave more unpredictably due to process variation, environmental changes and aging effects. Various variation-aware and adaptive desi...
Yubin Zhang, Haile Yu, Qiang Xu
DATE
2009
IEEE
163views Hardware» more  DATE 2009»
14 years 3 months ago
Fixed points for multi-cycle path detection
—Accurate timing analysis is crucial for obtaining the optimal clock frequency, and for other design stages such as power analysis. Most methods for estimating propagation delay ...
Vijay D'Silva, Daniel Kroening
ICCAD
1995
IEEE
68views Hardware» more  ICCAD 1995»
14 years 21 hour ago
Generating sparse partial inductance matrices with guaranteed stability
This paper proposes a definition of magnetic vector potential that can be used to evaluate sparse partial inductance matrices. Unlike the commonly applied procedure of discarding...
Byron Krauter, Lawrence T. Pileggi