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» Variation-tolerant circuits: circuit solutions and technique...
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ISQED
2011
IEEE
230views Hardware» more  ISQED 2011»
13 years 5 days ago
Constraint generation for software-based post-silicon bug masking with scalable resynthesis technique for constraint optimizatio
Due to the dramatic increase in design complexity, verifying the functional correctness of a circuit is becoming more difficult. Therefore, bugs may escape all verification effo...
Chia-Wei Chang, Hong-Zu Chou, Kai-Hui Chang, Jie-H...
CRYPTO
2010
Springer
188views Cryptology» more  CRYPTO 2010»
13 years 9 months ago
i-Hop Homomorphic Encryption and Rerandomizable Yao Circuits
Homomorphic encryption (HE) schemes enable computing functions on encrypted data, by means of a public Eval procedure that can be applied to ciphertexts. But the evaluated ciphert...
Craig Gentry, Shai Halevi, Vinod Vaikuntanathan
ICCAD
2003
IEEE
109views Hardware» more  ICCAD 2003»
14 years 5 months ago
Large-Scale Circuit Placement: Gap and Promise
Placement is one of the most important steps in the RTLto-GDSII synthesis process, as it directly defines the interconnects, which have become the bottleneck in circuit and syste...
Jason Cong, Tim Kong, Joseph R. Shinnerl, Min Xie,...
ICCD
2007
IEEE
161views Hardware» more  ICCD 2007»
14 years 5 months ago
Scan chain design for three-dimensional integrated circuits (3D ICs)
Scan chains are widely used to improve the testability of IC designs. In traditional 2D IC designs, various design techniques on the construction of scan chains have been proposed...
Xiaoxia Wu, Paul Falkenstern, Yuan Xie
ISQED
2003
IEEE
78views Hardware» more  ISQED 2003»
14 years 1 months ago
An Embedded IDDQ Testing Architecture and Technique
In this paper an embedded IDDQ testing architecture is presented that targets to overcome the excessive hardware overhead requirements in built-in current sensing based testing ap...
Y. Tsiatouhas, Th. Haniotakis, Angela Arapoyanni