Gate sizing and threshold voltage (Vt) assignment are popular techniques for circuit timing and power optimization. Existing methods, by and large, are either sensitivity-driven h...
Regularly structured design techniques can combat complexity on a variety of fronts. We present the Structured and Tuned Array Generation (STAG) design methodology, which provides...
Matthew M. Ziegler, Gary S. Ditlow, Stephen V. Kos...
Crosstalk faults have emerged as a significant mechanism for circuit failure. Long signal nets are of particular concern because they tend to have a higher coupling capacitance to...
— In this paper, we address the question of how to introduce new Quality-of-Service enhancements into the existing Internet. Specifically, dynamically shared circuitswitched/vir...
Xiuduan Fang, Malathi Veeraraghavan, Mark E. McGin...
As feature sizes decrease and chip sizes increase, the area and performance of chips become dominated by the interconnect. In spite of this trend, most existing synthesis systems ...