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» Variation-tolerant circuits: circuit solutions and technique...
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ISPD
2009
ACM
126views Hardware» more  ISPD 2009»
14 years 3 months ago
A new algorithm for simultaneous gate sizing and threshold voltage assignment
Gate sizing and threshold voltage (Vt) assignment are popular techniques for circuit timing and power optimization. Existing methods, by and large, are either sensitivity-driven h...
Yifang Liu, Jiang Hu
GLVLSI
2007
IEEE
140views VLSI» more  GLVLSI 2007»
14 years 2 months ago
Structured and tuned array generation (STAG) for high-performance random logic
Regularly structured design techniques can combat complexity on a variety of fronts. We present the Structured and Tuned Array Generation (STAG) design methodology, which provides...
Matthew M. Ziegler, Gary S. Ditlow, Stephen V. Kos...
TCAD
2010
130views more  TCAD 2010»
13 years 3 months ago
On ATPG for Multiple Aggressor Crosstalk Faults
Crosstalk faults have emerged as a significant mechanism for circuit failure. Long signal nets are of particular concern because they tend to have a higher coupling capacitance to...
Kunal P. Ganeshpure, Sandip Kundu
ICCCN
2007
IEEE
14 years 2 months ago
An overlay approach for enabling access to dynamically shared backbone GMPLS networks
— In this paper, we address the question of how to introduce new Quality-of-Service enhancements into the existing Internet. Specifically, dynamically shared circuitswitched/vir...
Xiuduan Fang, Malathi Veeraraghavan, Mark E. McGin...
ICCAD
1991
IEEE
100views Hardware» more  ICCAD 1991»
13 years 12 months ago
Layout Driven Logic Restructuring/Decomposition
As feature sizes decrease and chip sizes increase, the area and performance of chips become dominated by the interconnect. In spite of this trend, most existing synthesis systems ...
Massoud Pedram, Narasimha B. Bhat