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» Variation-tolerant circuits: circuit solutions and technique...
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ISQED
2005
IEEE
108views Hardware» more  ISQED 2005»
14 years 28 days ago
Error Analysis for the Support of Robust Voltage Scaling
Recently, a new Dynamic Voltage Scaling (DVS) scheme has been proposed that increases energy efficiency significantly by allowing the processor to operate at or slightly below the...
David Roberts, Todd M. Austin, David Blaauw, Trevo...
ASYNC
2003
IEEE
73views Hardware» more  ASYNC 2003»
14 years 19 days ago
Self-Timed Ring for Globally-Asynchronous Locally-Synchronous Systems
The lack of proven mechanisms for transferring data between multiple synchronous islands has been a major impediment for applying globally asynchronous locally synchronous (GALS) ...
Thomas Villiger, Hubert Kaeslin, Frank K. Gür...
FPGA
2001
ACM
152views FPGA» more  FPGA 2001»
13 years 12 months ago
A pipelined architecture for partitioned DWT based lossy image compression using FPGA's
Discrete wavelet transformations (DWT) followed by embedded zerotree encoding is a very efficient technique for image compression [2, 5, 4]. However, the algorithms proposed in l...
Jörg Ritter, Paul Molitor
DAC
1999
ACM
13 years 11 months ago
Test Generation for Gigahertz Processors Using an Automatic Functional Constraint Extractor
As the sizes of general and special purpose processors increase rapidly, generating high quality manufacturing tests which can be run at native speeds is becoming a serious proble...
Raghuram S. Tupuri, Arun Krishnamachary, Jacob A. ...
FCCM
1999
IEEE
111views VLSI» more  FCCM 1999»
13 years 11 months ago
Optimizing FPGA-Based Vector Product Designs
This paper presents a method, called multiple constant multiplier trees MCMTs, for producing optimized recon gurable hardware implementations of vector products. An algorithm for ...
Dan Benyamin, John D. Villasenor, Wayne Luk