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» Verification Environment for a SCMP Architecture
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ECBS
2007
IEEE
118views Hardware» more  ECBS 2007»
13 years 9 months ago
An Event-Driven Architecture for Fine Grained Intrusion Detection and Attack Aftermath Mitigation
In today’s computing environment, unauthorized accesses and misuse of critical data can be catastrophic to personal users, businesses, emergency services, and even national defe...
Jianfeng Peng, Chuan Feng, Haiyan Qiao, Jerzy W. R...
DAC
1998
ACM
14 years 8 months ago
Combining Theorem Proving and Trajectory Evaluation in an Industrial Environment
We describe the verification of the IM: a large, complex (12,000 gates and 1100 latches) circuit that detects and marks the boundaries between Intel architecture (IA-32) instructi...
Mark Aagaard, Robert B. Jones, Carl-Johan H. Seger
DAC
2001
ACM
14 years 8 months ago
A Framework for Object Oriented Hardware Specification, Verification, and Synthesis
We describe two things. First, we present a uniform framework for object oriented specification and verification of hardware. For this purpose the object oriented language `e'...
Tommy Kuhn, Tobias Oppold, Markus Winterholer, Wol...
MOBICOM
2006
ACM
14 years 1 months ago
Advanced TCP evaluation testbed on mixed wired internet and satellite environments
In this paper, we present our Advanced TCP Evaluation Testbed on Mixed Wired Internet and Satellite Environments. Categories and Subject Descriptors C.2.2 [Network Protocols]:–A...
Rosario Firrincieli, Carlo Caini, Cesar Marcondes,...
ASPDAC
2006
ACM
133views Hardware» more  ASPDAC 2006»
14 years 1 months ago
An SPU reference model for simulation, random test generation and verification
– An instruction set level reference model was developed for the development of synergistic processing unit (SPU) , which is one of the key components of the cell processor [1][2...
Yukio Watanabe, Balazs Sallay, Brad W. Michael, Da...