173 search results - page 22 / 35 » Verification of Distributed Hierarchical Components |
VLSID
2001
IEEE
14 years 7 months ago
2001
IEEE
In this paper we describe a hardware design method for memory and register arrays that allows the application of formal equivalence checking for comparing a high-level register tr...
CASES
2011
ACM
12 years 7 months ago
2011
ACM
This paper advocates a rigorously formal and compositional style for obtaining key performance and/or interface metrics of systems with real-time constraints. We propose a hierarc...
CAV
2006
Springer
13 years 11 months ago
2006
Springer
We present an approach for applying symmetry reduction techniques to probabilistic model checking, a formal verification method for the quantitative analysis of systems with stocha...
FM
1997
Springer
13 years 11 months ago
1997
Springer
: The widely accepted possible benefits of formal methods on the one hand and their minor use compared to informal or graphical description techniques on the other hand have repeat...
LISA
2008
13 years 9 months ago
2008
In recent times a new kind of computing system has emerged: a distributed infrastructure composed of multiple physical sites in different administrative domains. This model introd...