1219 search results - page 139 / 244 » Verification of Equivalent-Results Methods |
ASYNC
2002
IEEE
14 years 3 months ago
2002
IEEE
Wire and gate delays are accounted to have equal, or nearly equal, effect on circuit behavior in modern design techniques. This paper introduces a new approach to verify circuits ...
ICCAD
1998
IEEE
14 years 2 months ago
1998
IEEE
In this paper, an approach to symbolic model checking of process networks is introduced. It is based on interval decision diagrams (IDDs), a representation of multi-valued functio...
RTSS
1996
IEEE
14 years 2 months ago
1996
IEEE
We propose a method for reducing the number of clocks of a timed automaton by combining two algorithms. The first one consists in detecting active clocks, that is, those clocks wh...
ECAI
1994
Springer
14 years 2 months ago
1994
Springer
1 We develop a learning component for a theorem prover designed for verifying statements by mathematical induction. If the prover has found a proof, it is analyzed yielding a so-ca...
ASPDAC
2007
ACM
14 years 2 months ago
2007
ACM
- In this paper we showed the signal degradation parts in High-speed channel of FB-DiMM system. And we also showed possible countermeasure. For the verification propose and also fo...