1219 search results - page 38 / 244 » Verification of Equivalent-Results Methods |
FTRTFT
1992
Springer
14 years 24 days ago
1992
Springer
Real-Time Logic is a formal notation for reasoning about temporal behaviour. Z is a general purpose specification language, but lacks explicit features for expressing real-time co...
FMCAD
2000
Springer
14 years 10 days ago
2000
Springer
Abstract. We have formal verified a number of algorithms for evaluating transcendental functions in double-extended precision floating point arithmetic in the Intel
DAC
2002
ACM
14 years 9 months ago
2002
ACM
The ability to compute the parasitic inductance of the interconnect is critical to the timing verification of modern VLSI circuits. A challenging aspect of inductance extraction i...
ICSE
2008
IEEE-ACM
14 years 8 months ago
2008
IEEE-ACM
Software architecture evaluation has a crucial role in the life cycle of software intensive systems. In this paper we propose an approach to empower a software architecture evalua...
TII
2008
13 years 8 months ago
2008
Abstract--Safety analysis in Systems Engineering (SE) processes, as usually implemented, rarely relies on formal methods such as model checking since such techniques, however power...