1219 search results - page 84 / 244 » Verification of Equivalent-Results Methods |
UML
2004
Springer
14 years 3 months ago
2004
Springer
Abstract. In this paper, we propose a verification methodology for System-OnChip (SoC) design using Unified Modeling Language (UML). We introduce UML as a formal model to analyze a...
DSD
2002
IEEE
14 years 3 months ago
2002
IEEE
In this paper we describe a methodology for the formal verification of a DSP chip using the HOL theorem prover. We used an iterative method to specify both the behavioral and stru...
ACSD
1998
IEEE
14 years 2 months ago
1998
IEEE
This paper makes the idea of memory shadowing [5] applicable to symbolic ternary simulation. Memory shadowing, an extension of Burch and Dill's pipeline verification method [...
DATE
1998
IEEE
14 years 2 months ago
1998
IEEE
One of the main tasks within the high-level synthesis (HLS) process is the verification problem to prove automatically the correctness of the synthesis results. Currently, the res...
TPHOL
1998
IEEE
14 years 2 months ago
1998
IEEE
We show how extensible records with structural subtyping can be represented directly in Higher-Order Logic (HOL). Exploiting some specific properties of HOL, this encoding turns o...