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» Verification of System Level Model Transformations
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115
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ISMVL
2007
IEEE
104views Hardware» more  ISMVL 2007»
15 years 8 months ago
Evaluation of Toggle Coverage for MVL Circuits Specified in the SystemVerilog HDL
Designing modern circuits comprised of millions of gates is a very challenging task. Therefore new directions are investigated for efficient modeling and verification of such syst...
Mahsan Amoui, Daniel Große, Mitchell A. Thor...
140
Voted
EMSOFT
2001
Springer
15 years 7 months ago
Using Multiple Levels of Abstractions in Embedded Software Design
ltiple Levels of Abstractions in Embedded Software Design Jerry R. Burch1, Roberto Passerone1, and Alberto L. Sangiovanni-Vincentelli2 1 Cadence Berkeley Laboratories, Berkeley CA ...
Jerry R. Burch, Roberto Passerone, Alberto L. Sang...
ISSS
2002
IEEE
125views Hardware» more  ISSS 2002»
15 years 7 months ago
Design Experience of a Chip Multiprocessor Merlot and Expectation to Functional Verification
We have fabricated a Chip Multiprocessor prototype code-named Merlot to proof our novel speculative multithreading architecture. On Merlot, multiple threads provide wider issue wi...
Satoshi Matsushita
AMAST
2008
Springer
15 years 4 months ago
Towards an Efficient Implementation of Tree Automata Completion
Term Rewriting Systems (TRSs) are now commonly used as a modeling language for applications. In those rewriting based models, reachability analysis, i.e. proving or disproving that...
Emilie Balland, Yohan Boichut, Thomas Genet, Pierr...
IJISEC
2006
88views more  IJISEC 2006»
15 years 2 months ago
Requirements engineering for trust management: model, methodology, and reasoning
Abstract A number of recent proposals aim to incorporate security engineering into mainstream software engineering. Yet, capturing trust and security requirements at an organizatio...
Paolo Giorgini, Fabio Massacci, John Mylopoulos, N...