196 search results - page 19 / 40 » Verification of timing Properties of VHDL |
DATE
2006
IEEE
14 years 1 months ago
2006
IEEE
This paper presents an effective approach to formally verify SystemC designs. The approach translates SystemC models into a Petri-Net based representation. The Petri-net model is ...
CSL
2006
Springer
13 years 11 months ago
2006
Springer
In a previous work we introduced Dual Light Affine Logic (DLAL) ([BT04]) as a variant of Light Linear Logic suitable for guaranteeing complexity properties on lambda-calculus terms...
MSE
1999
IEEE
13 years 12 months ago
1999
IEEE
Intellectual property IP blocks are being created for reuse and marketed as a means of reducing the development time of complex designs. This in turn leads to a reduction in time ...
CAV
2001
Springer
13 years 11 months ago
2001
Springer
We consider the randomized consensus protocol of Aspnes and Herlihy for achieving agreement among N asynchronous processes that communicate via read/write shared registers. The alg...
DLT
2009
13 years 5 months ago
2009
Abstract. Temporal logics are a well investigated formalism for the specification and verification of reactive systems. Using formal verification techniques, we can ensure the corr...