196 search results - page 28 / 40 » Verification of timing Properties of VHDL |
ICCD
1996
IEEE
13 years 11 months ago
1996
IEEE
The Multi-Level Decomposition Diagrams (MLDDs) of this paper are a canonical representation of Boolean functions expliciting disjoint-support decompositions. MLDDs allow the reduc...
FORMATS
2010
Springer
13 years 5 months ago
2010
Springer
Abstract. We consider temporal logic formulae specifying constraints in continuous time and space on the behaviors of continuous and hybrid dynamical system admitting uncertain par...
VLSID
2010
IEEE
13 years 5 months ago
2010
IEEE
Directed test generation is important for the functional verification of complex system-on-chip designs. SAT based bounded model checking is promising for counterexample generatio...
TII
2008
13 years 7 months ago
2008
Abstract--Safety analysis in Systems Engineering (SE) processes, as usually implemented, rarely relies on formal methods such as model checking since such techniques, however power...
EJWCN
2010
13 years 2 months ago
2010
Model checking (MC) is a formal verification technique which has known and still knows a resounding success in the computer science community. Realizing that the distributed power...