196 search results - page 7 / 40 » Verification of timing Properties of VHDL |
ISQED
2003
IEEE
14 years 27 days ago
2003
IEEE
This paper describes the use of integer equations for high level modeling digital circuits for application of formal verification properties at this level. Most formal verificatio...
ECTEL
2007
Springer
13 years 11 months ago
2007
Springer
When a curriculum is proposed, it is important to verify at least three aspects: that the curriculum allows the achievement of the user's learning goals, that the curriculum i...
VLSID
2002
IEEE
14 years 8 months ago
2002
IEEE
Satisfiability of complex word-level formulas often arises as a problem in formal verification of hardware designs described at the register transfer level (RTL). Even though most...
PSTV
1993
13 years 9 months ago
1993
We present a new algorithm that can be used for solving the model−checking problem for linear−time temporal logic. This algorithm can be viewed as the combination of two exist...
FPL
2000
Springer
13 years 11 months ago
2000
Springer
This paper reports on a method for extending existing VHDL design and verification software available for the Xilinx Virtex series of FPGAs. It allows the designer to apply standa...