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EUROPAR
2001
Springer
14 years 6 days ago
Execution Latency Reduction via Variable Latency Pipeline and Instruction Reuse
Operand bypass logic might be one of the critical structures for future microprocessors to achieve high clock speed. The delay of the logic imposes the execution time budget to be ...
Toshinori Sato, Itsujiro Arita
WADS
2001
Springer
86views Algorithms» more  WADS 2001»
14 years 4 days ago
Practical Approximation Algorithms for Separable Packing Linear Programs
Abstract. We describe fully polynomial time approximation schemes for generalized multicommodity flow problems arising in VLSI applications such as Global Routing via Buffer Block...
Feodor F. Dragan, Andrew B. Kahng, Ion I. Mandoiu,...
FCCM
2000
IEEE
105views VLSI» more  FCCM 2000»
14 years 4 days ago
Configuration Relocation and Defragmentation for Reconfigurable Computing
Custom computing systems exhibit significant speedups over traditional microprocessors by mapping compute-intensive sections of a program to reconfigurable logic [Hauck98]. Howeve...
Katherine Compton, James Cooley, Stephen Knol, Sco...
MICRO
2000
IEEE
80views Hardware» more  MICRO 2000»
14 years 3 days ago
Silent stores for free
Silent store instructions write values that exactly match the values that are already stored at the memory address that is being written. A recent study reveals that significant ...
Kevin M. Lepak, Mikko H. Lipasti
PLDI
2000
ACM
14 years 2 days ago
Exploiting superword level parallelism with multimedia instruction sets
Increasing focus on multimedia applications has prompted the addition of multimedia extensions to most existing general purpose microprocessors. This added functionality comes pri...
Samuel Larsen, Saman P. Amarasinghe