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ETS
2011
IEEE
224views Hardware» more  ETS 2011»
12 years 7 months ago
AVF Analysis Acceleration via Hierarchical Fault Pruning
—The notion of Architectural Vulnerability Factor (AVF) has been extensively used by designers to evaluate various aspects of design robustness. While AVF is a very accurate way ...
Michail Maniatakos, Chandra Tirumurti, Abhijit Jas...
SIGMETRICS
2006
ACM
116views Hardware» more  SIGMETRICS 2006»
14 years 1 months ago
Applying architectural vulnerability Analysis to hard faults in the microprocessor
In this paper, we present a new metric, Hard-Fault Architectural Vulnerability Factor (H-AVF), to allow designers to more effectively compare alternate hard-fault tolerance scheme...
Fred A. Bower, Derek Hower, Mahmut Yilmaz, Daniel ...
DAC
1999
ACM
14 years 7 days ago
On-Chip Inductance Issues in Multiconductor Systems
As the family of Alpha microprocessors continues to scale into more advanced technologies with very high frequency edge rates and multiple layers of interconnect, the issue of cha...
Shannon V. Morton
PLDI
1994
ACM
14 years 15 hour ago
Memory Access Coalescing: A technique for Eliminating Redundant memory Accesses
As microprocessor speeds increase, memory bandwidth is increasing y the performance bottleneck for microprocessors. This has occurred because innovation and technological improvem...
Jack W. Davidson, Sanjay Jinturkar
ISLPED
2004
ACM
102views Hardware» more  ISLPED 2004»
14 years 1 months ago
Microarchitectural power modeling techniques for deep sub-micron microprocessors
The need to perform early design studies that combine architectural simulation with power estimation has become critical as power has become a design constraint whose importance h...
Nam Sung Kim, Taeho Kgil, Valeria Bertacco, Todd M...