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» Verification-Aware Microprocessor Design
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VLSID
2007
IEEE
97views VLSI» more  VLSID 2007»
14 years 8 months ago
Efficient Microprocessor Verification using Antecedent Conditioned Slicing
We present a technique for automatic verification of pipelined microprocessors using model checking. Antecedent conditioned slicing is an efficient abstraction technique for hardw...
Shobha Vasudevan, Vinod Viswanath, Jacob A. Abraha...
HPCA
2003
IEEE
14 years 8 months ago
Deterministic Clock Gating for Microprocessor Power Reduction
With the scaling of technology and the need for higher performance and more functionality, power dissipation is becoming a major bottleneck for microprocessor designs. Pipeline ba...
Hai Li, Swarup Bhunia, Yiran Chen, T. N. Vijaykuma...
ISLPED
2006
ACM
73views Hardware» more  ISLPED 2006»
14 years 1 months ago
Substituting associative load queue with simple hash tables in out-of-order microprocessors
Buffering more in-flight instructions in an out-of-order microprocessor is a straightforward and effective method to help tolerate the long latencies generally associated with ...
Alok Garg, Fernando Castro, Michael C. Huang, Dani...
TPDS
2008
89views more  TPDS 2008»
13 years 7 months ago
Power/Performance/Thermal Design-Space Exploration for Multicore Architectures
Multicore architectures have been ruling the recent microprocessor design trend. This is due to different reasons: better performance, thread-level parallelism bounds in modern app...
Matteo Monchiero, Ramon Canal, Antonio Gonzá...
MICRO
2007
IEEE
71views Hardware» more  MICRO 2007»
13 years 7 months ago
Effective Optimistic-Checker Tandem Core Design through Architectural Pruning
Design complexity is rapidly becoming a limiting factor in the design of modern, high-performance microprocessors. This paper introduces an optimization technique to improve the e...
Francisco J. Mesa-Martinez, Jose Renau