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CODES
2008
IEEE
13 years 9 months ago
Profiling of lossless-compression algorithms for a novel biomedical-implant architecture
In view of a booming market for microelectronic implants, our ongoing research work is focusing on the specification and design of a novel biomedical microprocessor core targeting...
Christos Strydis, Georgi Gaydadjiev
TCAD
2008
172views more  TCAD 2008»
13 years 7 months ago
General Methodology for Soft-Error-Aware Power Optimization Using Gate Sizing
Power consumption has emerged as the premier and most constraining aspect in modern microprocessor and application-specific designs. Gate sizing has been shown to be one of the mos...
Foad Dabiri, Ani Nahapetian, Tammara Massey, Miodr...
ISCAS
2005
IEEE
115views Hardware» more  ISCAS 2005»
14 years 1 months ago
Power-aware slack distribution for hierarchical VLSI design
Abstract— Hierarchical design plays an important role in microprocessor and ASIC domains where design complexity limits design productivity and tool capacity. Slack distribution,...
Hyung-Ock Kim, Youngsoo Shin
ARITH
1999
IEEE
14 years 5 days ago
Floating-Point Unit in Standard Cell Design with 116 Bit Wide Dataflow
The floating-point unit of a S/390 CMOS microprocessor is described. It contains a 116 bit fraction dataflow for addition and subtraction and a 64 bit-wide multiplier. Besides the...
Guenter Gerwig, Michael Kroener
ICCD
2006
IEEE
133views Hardware» more  ICCD 2006»
14 years 4 months ago
Patching Processor Design Errors
— Microprocessors can have design errors that escape the test and validation process. The cost to rectify these errors after shipping the processors can be very expensive as it m...
Satish Narayanasamy, Bruce Carneal, Brad Calder