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» Verification-Aware Microprocessor Design
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ISCA
2002
IEEE
128views Hardware» more  ISCA 2002»
14 years 23 days ago
Detailed Design and Evaluation of Redundant Multithreading Alternatives
Exponential growth in the number of on-chip transistors, coupled with reductions in voltage levels, makes each generation of microprocessors increasingly vulnerable to transient f...
Shubhendu S. Mukherjee, Michael Kontz, Steven K. R...
MICRO
2000
IEEE
84views Hardware» more  MICRO 2000»
14 years 6 days ago
The impact of delay on the design of branch predictors
Modern microprocessors employ increasingly complicated branch predictors to achieve instruction fetch bandwidth that is sufficient for wide out-of-order execution cores. While ex...
Daniel A. Jiménez, Stephen W. Keckler, Calv...
HPCA
2005
IEEE
14 years 1 months ago
Exploring the Design Space of Power-Aware Opto-Electronic Networked Systems
As microprocessors become increasingly interconnected, the power consumed by the interconnection network can no longer be ignored. Moreover, with demand for link bandwidth increas...
Xuning Chen, Li-Shiuan Peh, Gu-Yeon Wei, Yue-Kai H...
IEEEPACT
2005
IEEE
14 years 1 months ago
Design and Implementation of a Compiler Framework for Helper Threading on Multi-core Processors
Helper threading is a technique that utilizes a second core or logical processor in a multi-threaded system to improve the performance of the main thread. A helper thread executes...
Yonghong Song, Spiros Kalogeropulos, Partha Tiruma...
COOPIS
2002
IEEE
14 years 24 days ago
The Design and Performance of the jRate Real-Time Java Implementation
Over 90 percent of all microprocessors are now used for realtime and embedded applications. Since the behavior of these applications is often constrained by the physical world, it...
Angelo Corsaro, Douglas C. Schmidt