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ICCD
2004
IEEE
115views Hardware» more  ICCD 2004»
14 years 4 months ago
Generating Monitor Circuits for Simulation-Friendly GSTE Assertion Graphs
Formal and dynamic (simulation, emulation, etc.) verification techniques are both needed to deal with the overall challenge of verification. Ideally, the same specification/tes...
Kelvin Ng, Alan J. Hu, Jin Yang
ISPASS
2010
IEEE
14 years 2 months ago
Memphis: Finding and fixing NUMA-related performance problems on multi-core platforms
—Until recently, most high-end scientific applications have been immune to performance problems caused by NonUniform Memory Access (NUMA). However, current trends in micro-proces...
Collin McCurdy, Jeffrey S. Vetter
ISQED
2009
IEEE
86views Hardware» more  ISQED 2009»
14 years 2 months ago
Uncriticality-directed scheduling for tackling variation and power challenges
The advance in semiconductor technologies presents the serious problem of parameter variations. They affect threshold voltage of transistors and thus circuit delay has variability...
Toshinori Sato, Shingo Watanabe
DATE
2009
IEEE
110views Hardware» more  DATE 2009»
14 years 2 months ago
Light NUCA: A proposal for bridging the inter-cache latency gap
Abstract—To deal with the “memory wall” problem, microprocessors include large secondary on-chip caches. But as these caches enlarge, they originate a new latency gap between...
Darío Suárez Gracia, Teresa Monreal,...
FCCM
2009
IEEE
171views VLSI» more  FCCM 2009»
14 years 2 months ago
Accelerating SPICE Model-Evaluation using FPGAs
—Single-FPGA spatial implementations can provide an order of magnitude speedup over sequential microprocessor implementations for data-parallel, floating-point computation in SP...
Nachiket Kapre, André DeHon