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» Verification-Aware Microprocessor Design
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DAC
1994
ACM
14 years 1 months ago
Synthesis of Instruction Sets for Pipelined Microprocessors
We present a systematic approach to synthesize an instruction set such that the given application software can be efficiently mapped to a parameterized, pipelined microarchitectur...
Ing-Jer Huang, Alvin M. Despain
FPGA
2008
ACM
174views FPGA» more  FPGA 2008»
13 years 10 months ago
When FPGAs are better at floating-point than microprocessors
It has been shown that FPGAs could outperform high-end microprocessors on floating-point computations thanks to massive parallelism. However, most previous studies re-implement in...
Florent de Dinechin, Jérémie Detrey,...
VLSID
2000
IEEE
135views VLSI» more  VLSID 2000»
14 years 15 days ago
Performance and Functional Verification of Microprocessors
We address the problem of verifying the correctness of pre-silicon models of a microprocessor. We touch on the latest advances in this area by considering two different aspects of...
Pradip Bose, Jacob A. Abraham
CAINE
2003
13 years 10 months ago
An Issue Logic for Superscalar Microprocessors
In order to enhance the computer performance, nowadays microprocessors use Superscalar architecture. But the Superscalar architecture is unable to enhance the performance effectiv...
Feng-Jiann Shiao, Jong-Jiann Shieh
ASPLOS
1989
ACM
14 years 1 months ago
Architecture and Compiler Tradeoffs for a Long Instruction Word Microprocessor
A very long instruction word (VLIW) processorexploits parallelism by controlling multiple operations in a single instruction word. This paper describes the architecture and compil...
Robert Cohn, Thomas R. Gross, Monica S. Lam, P. S....