2838 search results - page 127 / 568 » Verifying Controlled Components |
ASYNC
2002
IEEE
14 years 3 months ago
2002
IEEE
Wire and gate delays are accounted to have equal, or nearly equal, effect on circuit behavior in modern design techniques. This paper introduces a new approach to verify circuits ...
ISPD
2000
ACM
14 years 2 months ago
2000
ACM
We propose a gate resizing method for delay and power optimization that is based on statistical static timing analysis. Our method focuses on the component of timing uncertainties...
ECAI
1994
Springer
14 years 2 months ago
1994
Springer
1 We develop a learning component for a theorem prover designed for verifying statements by mathematical induction. If the prover has found a proof, it is analyzed yielding a so-ca...
FMCO
2007
Springer
14 years 2 months ago
2007
Springer
This paper describes a core component of Mobius' Trusted Code Base, the Mobius base logic. This program logic facilitates the transmission of certificates that are generated u...
SNPD
2004
13 years 11 months ago
2004
A typical problem formal verification faces is the size of the model of a system being verified. Even for a small system, the state space of the model tends to grow exponentially (...