A performance optimization method by gate sizing using statistical static timing analysis

We propose a gate resizing method for delay and power optimization that is based on statistical static timing analysis. Our method focuses on the component of timing uncertainties due to local random fluctuation. Utilizing our method, over-design of a circuit can be eliminated and high-performance and high-reliability LSI design can be realized. The effectiveness of our method is examined by 6 benchmark circuits. We verify that our method can reduce delay and power dissipation from the circuits optimized without the consideration of fluctuation.

• Type: Conference
• Year: 2000
• Where: ISPD
• Authors: Masanori Hashimoto, Hidetoshi Onodera
• Keywords: Gate Resizing Method, Hardware, ISPD 2000, Local Random Fluctuation, Statistical Static Timing Analysis