Sciweavers

72 search results - page 2 / 15
» Verifying Local Transformations on Relaxed Memory Models
Sort
View
HPCA
1999
IEEE
14 years 3 months ago
Using Lamport Clocks to Reason about Relaxed Memory Models
Cache coherence protocols of current shared-memory multiprocessors are difficult to verify. Our previous work proposed an extension of Lamport's logical clocks for showing th...
Anne Condon, Mark D. Hill, Manoj Plakal, Daniel J....
CAV
2008
Springer
157views Hardware» more  CAV 2008»
14 years 26 days ago
Effective Program Verification for Relaxed Memory Models
Program verification for relaxed memory models is hard. The high degree of nondeterminism in such models challenges standard verification techniques. This paper proposes a new veri...
Sebastian Burckhardt, Madanlal Musuvathi
MICRO
2008
IEEE
137views Hardware» more  MICRO 2008»
13 years 10 months ago
Verification of chip multiprocessor memory systems using a relaxed scoreboard
Verification of chip multiprocessor memory systems remains challenging. While formal methods have been used to validate protocols, simulation is still the dominant method used to ...
Ofer Shacham, Megan Wachs, Alex Solomatnikov, Amin...
TPHOL
2009
IEEE
14 years 5 months ago
A Better x86 Memory Model: x86-TSO
Abstract. Real multiprocessors do not provide the sequentially consistent memory that is assumed by most work on semantics and verification. Instead, they have relaxed memory mode...
Scott Owens, Susmit Sarkar, Peter Sewell
CASES
2008
ACM
14 years 26 days ago
A light-weight cache-based fault detection and checkpointing scheme for MPSoCs enabling relaxed execution synchronization
While technology advances have made MPSoCs a standard architecture for embedded systems, their applicability is increasingly being challenged by dramatic increases in the amount o...
Chengmo Yang, Alex Orailoglu