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» Verifying Progress in Timed Systems
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ICNP
2007
IEEE
14 years 3 months ago
Loss and Delay Accountability for the Internet
— The Internet provides no information on the fate of transmitted packets, and end systems cannot determine who is responsible for dropping or delaying their traffic. As a resul...
Katerina J. Argyraki, Petros Maniatis, O. Irzak, S...
ISCAS
2007
IEEE
141views Hardware» more  ISCAS 2007»
14 years 3 months ago
Analog Emulation of a Reconfigurable Tap Changing Transformer
—Accurate analog models of power system components are required in order to realize an analog computation engine for power systems. Analog computation is an area of continued int...
Aaron St. Leger, Juan C. Jimenez, Agung Fu, Sanal ...
CSMR
2006
IEEE
14 years 3 months ago
IntensiVE, a toolsuite for documenting and checking structural source-code regularities
As size and complexity of software systems increase, preserving the design and specification of their implementation structure gains importance in order to maintain the evolvabil...
Kim Mens, Andy Kellens
PADS
2003
ACM
14 years 2 months ago
DVS: An Object-Oriented Framework for Distributed Verilog Simulation
There is a wide-spread usage of hardware design languages(HDL) to speed up the time-to-market for the design of modern digital systems. Verification engineers can simulate hardwa...
Lijun Li, Hai Huang, Carl Tropper
KI
1999
Springer
14 years 1 months ago
Revising Nonmonotonic Theories: The Case of Defeasible Logic
Abstract. The revision and transformation of knowledge is widely recognized as a key issue in knowledge representation and reasoning. Reasons for the importance of this topic are t...
David Billington, Grigoris Antoniou, Guido Governa...