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ARVLSI
1997
IEEE
105views VLSI» more  ARVLSI 1997»
14 years 2 months ago
An Embedded DRAM for CMOS ASICs
The growing gap between on-chip gates and off-chip I/O bandwidth argues for ever larger amounts of on-chip memory. Emerging portable consumer technology, such as digital cameras, ...
John Poulton
VLSID
1997
IEEE
98views VLSI» more  VLSID 1997»
14 years 2 months ago
Synthesis for Logical Initializability of Synchronous Finite State Machines
—Logical initializability is the property of a gate-level circuit whereby it can be driven to a unique start state when simulated by a three-valued (0, 1, ) simulator. In practic...
Montek Singh, Steven M. Nowick
GLVLSI
2009
IEEE
262views VLSI» more  GLVLSI 2009»
13 years 7 months ago
Power distribution paths in 3-D ICS
Distributing power and ground to a vertically integrated system is a complex and difficult task. Interplane communication and power delivery are achieved by through silicon vias (...
Vasilis F. Pavlidis, Giovanni De Micheli
ISCAS
2008
IEEE
134views Hardware» more  ISCAS 2008»
14 years 4 months ago
2xVDD-tolerant crystal oscillator circuit realized with 1xVDD CMOS devices without gate-oxide reliability issue
—A new 2xVDD-tolerant crystal oscillator circuit realized with 1xVDD CMOS devices without suffering gateoxide reliability issue is proposed, which is one of the key mixedvoltage ...
Ming-Dou Ker, Tzu-Ming Wang, Hung-Tai Liao
ASIACRYPT
2010
Springer
13 years 8 months ago
Short Non-interactive Zero-Knowledge Proofs
We show that probabilistically checkable proofs can be used to shorten non-interactive zero-knowledge proofs. We obtain publicly verifiable non-interactive zero-knowledge proofs fo...
Jens Groth