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» Verifying VLSI Circuits
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ICEC
1994
147views more  ICEC 1994»
13 years 8 months ago
VLSI Circuit Synthesis Using a Parallel Genetic Algorithm
A parallel implementation of a genetic algorithm used to evolve simple analog VLSI circuits is described. The parallel computer system consisted of twenty distributed SPARC workst...
Mike Davis, Luoping Liu, John G. Elias
GLVLSI
2007
IEEE
151views VLSI» more  GLVLSI 2007»
13 years 11 months ago
Hand-in-hand verification of high-level synthesis
This paper describes a formal verification methodology of highnthesis (HLS) process. The abstraction level of the input to HLS is so high compared to that of the output that the v...
Chandan Karfa, Dipankar Sarkar, Chittaranjan A. Ma...
DAC
2002
ACM
14 years 8 months ago
Dynamic and leakage power reduction in MTCMOS circuits using an automated efficient gate clustering technique
Reducing power dissipation is one of the most principle subjects in VLSI design today. Scaling causes subthreshold leakage currents to become a large component of total power diss...
Mohab Anis, Mohamed Mahmoud, Mohamed I. Elmasry, S...
DFT
2004
IEEE
95views VLSI» more  DFT 2004»
13 years 11 months ago
Mixed Loopback BiST for RF Digital Transceivers
In this paper we analyze the performance of a mixed built-in-self-test (BiST) for RF IC digital transceivers, where a baseband processor can be used both as a test pattern generat...
Jerzy Dabrowski, Javier Gonzalez Bayon
SBCCI
2005
ACM
86views VLSI» more  SBCCI 2005»
14 years 1 months ago
Ultra-low power CMOS cells for temperature sensors
Temperature sensors and voltage references require cells that generate both PTAT (Proportional To Absolute Temperature) and NTC (Negative Temperature Coefficient) voltages. We pre...
Conrado Rossi, Pablo Aguirre